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27 #ifndef ADRF6660_MAP_H
28 #define ADRF6660_MAP_H
115 #define MASK_SOFTRESET_ 0b10000000
116 #define MASK_LSB_FIRST_ 0b01000000
117 #define MASK_ENDIAN_ 0b00100000
118 #define MASK_SDOACTIVE_ 0b00010000
119 #define MASK_SDOACTIVE 0b00001000
120 #define MASK_ENDIAN 0b00000100
121 #define MASK_LSB_FIRST 0b00000010
122 #define MASK_SOFTRESET 0b00000001
123 #define SHIFT_SOFTRESET_ 7
124 #define SHIFT_LSB_FIRST_ 6
125 #define SHIFT_ENDIAN_ 5
126 #define SHIFT_SDOACTIVE_ 4
127 #define SHIFT_SDOACTIVE 3
128 #define SHIFT_ENDIAN 2
129 #define SHIFT_LSB_FIRST 1
130 #define SHIFT_SOFTRESET 0
132 #define MASK_SINGLE_INSTRUCTION 0b10000000
133 #define MASK_CSB_STALL 0b01000000
134 #define MASK_MASTER_SLAVE_RB 0b00100000
135 #define MASK_SOFTRESET_B 0b00000110
136 #define MASK_MASTER_SLAVE_TRANSFER 0b00000001
137 #define SHIFT_SINGLE_INSTRUCTION 7
138 #define SHIFT_CSB_STALL 6
139 #define SHIFT_MASTER_SLAVE_RB 5
140 #define SHIFT_SOFTRESET_B 1
141 #define SHIFT_MASTER_SLAVE_TRANSFER 0
143 #define MASK_OPERATING_MODE 0b00001100
144 #define MASK_POWER_MODE 0b00000011
145 #define SHIFT_OPERATING_MODE 2
146 #define SHIFT_POWER_MODE 0
148 #define MASK_CHIPTYPE 0b11111111
149 #define SHIFT_CHIPTYPE 0
151 #define MASK_PRODUCT_ID_1 0b11111111
152 #define SHIFT_PRODUCT_ID_1 0
154 #define MASK_PRODUCT_ID_2 0b11111111
155 #define SHIFT_PRODUCT_ID_2 0
157 #define MASK_SCRATCHPAD 0b11111111
158 #define SHIFT_SCRATCHPAD 0
160 #define MASK_SPI_VER 0b11111111
161 #define SHIFT_SPI_VER 0
163 #define MASK_VENDOR_ID7_0 0b11111111
164 #define SHIFT_VENDOR_ID7_0 0
166 #define MASK_VENDOR_ID15_8 0b11111111
167 #define SHIFT_VENDOR_ID15_8 0
169 #define MASK_DVGA_CH2_RSTB 0b00000010
170 #define MASK_DVGA_CH1_RSTB 0b00000001
171 #define SHIFT_DVGA_CH2_RSTB 1
172 #define SHIFT_DVGA_CH1_RSTB 0
174 #define MASK_ATTEN_READBACK_CH1 0b11111111
175 #define SHIFT_ATTEN_READBACK_CH1 0
177 #define MASK_ATTEN_READBACK_CH2 0b11111111
178 #define SHIFT_ATTEN_READBACK_CH2 0
180 #define MASK_DVGA_TRIM_READBACK_CH1 0b11111111
181 #define SHIFT_DVGA_TRIM_READBACK_CH1 0
183 #define MASK_DVGA_TRIM_READBACK_CH2 0b11111111
184 #define SHIFT_DVGA_TRIM_READBACK_CH2 0
186 #define MASK_DVGA_ENB_CH2 0b10000000
187 #define MASK_DVGA_ENB_CH1 0b01000000
188 #define MASK_IF_ENB_CH2 0b00100000
189 #define MASK_IF_ENB_CH1 0b00010000
190 #define MASK_LO_STG23_ENB_CH2 0b00001000
191 #define MASK_LO_STG23_ENB_CH1 0b00000100
192 #define MASK_LO_STG1_ENB 0b00000010
193 #define MASK_BYPASS_TDD 0b00000001
194 #define SHIFT_DVGA_ENB_CH2 7
195 #define SHIFT_DVGA_ENB_CH1 6
196 #define SHIFT_IF_ENB_CH2 5
197 #define SHIFT_IF_ENB_CH1 4
198 #define SHIFT_LO_STG23_ENB_CH2 3
199 #define SHIFT_LO_STG23_ENB_CH1 2
200 #define SHIFT_LO_STG1_ENB 1
201 #define SHIFT_BYPASS_TDD 0
203 #define MASK_IFLIN_BIAS_EN 0b00100000
204 #define MASK_IFMAIN_BIAS_EN 0b00010000
205 #define MASK_SPI_18_33_SEL 0b00000001
206 #define SHIFT_IFLIN_BIAS_EN 5
207 #define SHIFT_IFMAIN_BIAS_EN 4
208 #define SHIFT_SPI_18_33_SEL 0
210 #define MASK_PLL_ENB_CH12_MASK 0b10000000
211 #define MASK_DVGA_ENB_CH2_MASK 0b01000000
212 #define MASK_DVGA_ENB_CH1_MASK 0b00100000
213 #define MASK_IF_ENB_CH2_MASK 0b00010000
214 #define MASK_IF_ENB_CH1_MASK 0b00001000
215 #define MASK_LO_STG23_ENB_CH2_MASK 0b00000100
216 #define MASK_LO_STG23_ENB_CH1_MASK 0b00000010
217 #define MASK_LO_STG1_ENB_MASK 0b00000001
218 #define SHIFT_PLL_ENB_CH12_MASK 7
219 #define SHIFT_DVGA_ENB_CH2_MASK 6
220 #define SHIFT_DVGA_ENB_CH1_MASK 5
221 #define SHIFT_IF_ENB_CH2_MASK 4
222 #define SHIFT_IF_ENB_CH1_MASK 3
223 #define SHIFT_LO_STG23_ENB_CH2_MASK 2
224 #define SHIFT_LO_STG23_ENB_CH1_MASK 1
225 #define SHIFT_LO_STG1_ENB_MASK 0
227 #define MASK_DVGA_5V_SEL 0b10000000
228 #define MASK_DVGA_FA_STEP 0b01100000
229 #define MASK_DVGA_UPDN_STEP 0b00011000
230 #define MASK_DVGA_GAIN_MODE 0b00000111
231 #define SHIFT_DVGA_5V_SEL 7
232 #define SHIFT_DVGA_FA_STEP 5
233 #define SHIFT_DVGA_UPDN_STEP 3
234 #define SHIFT_DVGA_GAIN_MODE 0
236 #define MASK_DVGA_HP_SEL 0b01000000
237 #define MASK_DVGA_GAIN_CH1 0b00111111
238 #define SHIFT_DVGA_HP_SEL 6
239 #define SHIFT_DVGA_GAIN_CH1 0
241 #define MASK_DVGA_GAIN_CH2 0b00111111
242 #define SHIFT_DVGA_GAIN_CH2 0
244 #define MASK_LPF2_OVERRIDE 0b01110000
245 #define MASK_LPF1_OVERRIDE 0b00001110
246 #define MASK_LPF_DPLX_EN_OVERRIDE 0b00000001
247 #define SHIFT_LPF2_OVERRIDE 4
248 #define SHIFT_LPF1_OVERRIDE 1
249 #define SHIFT_LPF_DPLX_EN_OVERRIDE 0
251 #define MASK_IFMAIN_BIAS_OVERRIDE 0b00001111
252 #define SHIFT_IFMAIN_BIAS_OVERRIDE 0
254 #define MASK_IFLIN_BIAS_OVERRIDE 0b00001111
255 #define SHIFT_IFLIN_BIAS_OVERRIDE 0
257 #define MASK_VGS_OVERRIDE 0b00001111
258 #define SHIFT_VGS_OVERRIDE 0
260 #define MASK_DVGA_TRIM_LP_3V_CH1_OVERRIDE 0b00011111
261 #define SHIFTDVGA_TRIM_LP_3V_CH1_OVERRIDE 0
263 #define MASK_DVGA_TRIM_HP_3V_CH1_OVERRIDE 0b00011111
264 #define SHIFTDVGA_TRIM_HP_3V_CH1_OVERRIDE 0
266 #define MASK_DVGA_TRIM_LP_5V_CH1_OVERRIDE 0b00011111
267 #define SHIFTDVGA_TRIM_LP_5V_CH1_OVERRIDE 0
269 #define MASK_DVGA_TRIM_HP_5V_CH1_OVERRIDE 0b00011111
270 #define SHIFTDVGA_TRIM_HP_5V_CH1_OVERRIDE 0
272 #define MASK_DVGA_TRIM_LP_3V_CH2_OVERRIDE 0b00011111
273 #define SHIFTDVGA_TRIM_LP_3V_CH2_OVERRIDE 0
275 #define MASK_DVGA_TRIM_HP_3V_CH2_OVERRIDE 0b00011111
276 #define SHIFTDVGA_TRIM_HP_3V_CH2_OVERRIDE 0
278 #define MASK_DVGA_TRIM_LP_5V_CH2_OVERRIDE 0b00011111
279 #define SHIFTDVGA_TRIM_LP_5V_CH2_OVERRIDE 0
281 #define MASK_DVGA_TRIM_HP_5V_CH2_OVERRIDE 0b00011111
282 #define SHIFTDVGA_TRIM_HP_5V_CH2_OVERRIDE 0
284 #define MASK_SPARE2_OVERRIDE_SEL 0b10000000
285 #define MASK_SPARE1_OVERRIDE_SEL 0b01000000
286 #define MASK_DVGA_TRIM_CH2_OVERRIDE_SEL 0b00100000
287 #define MASK_DVGA_TRIM_CH1_OVERRIDE_SEL 0b00010000
288 #define MASK_VGS_OVERRIDE_SEL 0b00001000
289 #define MASK_IFLIN_TRIM_OVERRIDE_SEL 0b00000100
290 #define MASK_IFMAIN_TRIM_OVERRIDE_SEL 0b00000010
291 #define MASK_LPF_TRIM_OVERRIDE_SEL 0b00000001
292 #define SHIFT_SPARE2_OVERRIDE_SEL 7
293 #define SHIFT_SPARE1_OVERRIDE_SEL 6
294 #define SHIFT_DVGA_TRIM_CH2_OVERRIDE_SEL 5
295 #define SHIFT_DVGA_TRIM_CH1_OVERRIDE_SEL 4
296 #define SHIFT_VGS_OVERRIDE_SEL 3
297 #define SHIFT_IFLIN_TRIM_OVERRIDE_SEL 2
298 #define SHIFT_IFMAIN_TRIM_OVERRIDE_SEL 1
299 #define SHIFT_LPF_TRIM_OVERRIDE_SEL 0
301 #define MASK_ARSTB_BLOCK_LKD 0b01000000
302 #define MASK_ARSTB_BLOCK_AUTOCAL 0b00100000
303 #define MASK_ARSTB_BLOCK_NDIV 0b00010000
304 #define MASK_ARSTB_BLOCK_RDIV 0b00001000
305 #define MASK_ARSTB_BLOCK_DSMOSTG 0b00000100
306 #define MASK_ARSTB_BLOCK_DSMCORE 0b00000010
307 #define MASK_ARSTB_BLOCK_DSMALL 0b00000001
308 #define SHIFT_ARSTB_BLOCK_LKD 6
309 #define SHIFT_ARSTB_BLOCK_AUTOCAL 5
310 #define SHIFT_ARSTB_BLOCK_NDIV 4
311 #define SHIFT_ARSTB_BLOCK_RDIV 3
312 #define SHIFT_ARSTB_BLOCK_DSMOSTG 2
313 #define SHIFT_ARSTB_BLOCK_DSMCORE 1
314 #define SHIFT_ARSTB_BLOCK_DSMALL 0
316 #define MASK_GPO1_BLK_SEL 0b01111000
317 #define MASK_GPO1_ENABLE 0b00000001
318 #define SHIFT__GPO1_BLK_SEL 3
319 #define SHIFT__GPO1_ENABLE 0
321 #define MASK_GPO1_SGNL_SEL 0b11111111
322 #define SHIFT_GPO1_SGNL_SEL 0
324 #define MASK_TRM_MIXLODRV_DRV_POUT 0b00011000
325 #define MASK_TRM_XLODRV_DRV_POUT 0b00000110
326 #define SHIFT_TRM_MIXLODRV_DRV_POUT 3
327 #define SHIFT_TRM_XLODRV_DRV_POUT 1
329 #define MASK_INT_DIV7_0 0b11111111
330 #define SHIFT_INT_DIV7_0 0
332 #define MASK_INT_DIV15_8 0b11111111
333 #define SHIFT_INT_DIV15_8 0
335 #define MASK_FRAC7_0 0b11111111
336 #define SHIFT_FRAC7_0 0
338 #define MASK_FRAC15_8 0b11111111
339 #define SHIFT_FRAC15_8 0
341 #define MASK_FRAC23_16 0b11111111
342 #define SHIFT_FRAC23_16 0
344 #define MASK_PHASE7_0 0b11111111
345 #define SHIFT_PHASE7_0 0
347 #define MASK_PHASE15_8 0b11111111
348 #define SHIFT_PHASE15_8 0
350 #define MASK_PHASE23_16 0b11111111
351 #define SHIFT_PHASE23_16 0
353 #define MASK_MOD7_0 0b11111111
354 #define SHIFT_MOD7_0 0
356 #define MASK_MOD13_8 0b00111111
357 #define SHIFT_MOD13_8 0
359 #define MASK_PRE_SEL 0b00000010
360 #define MASK_EN_FBDIV 0b00000001
361 #define SHIFT_PRE_SEL 1
362 #define SHIFT_EN_FBDIV 0
364 #define MASK_R_DIV 0b01111111
365 #define SHIFT_R_DIV 0
367 #define MASK_DOUBLER_EN 0b00001000
368 #define MASK_RDIV2_SEL 0b00000001
369 #define SHIFT_DOUBLER_EN 3
370 #define SHIFT_RDIV2_SEL 0
372 #define MASK_LD_BIAS 0b11000000
373 #define MASK_LDP 0b00111000
374 #define SHIFT_LD_BIAS 6
377 #define MASK_SI_VCO_SEL 0b00001111
378 #define SHIFT_SI_VCO_SEL 0
380 #define MASK_DISABLE_CAL 0b01000000
381 #define SHIFT_DISABLE_CAL 6
383 #define MASK_SD_EN_FRAC0 0b00100000
384 #define MASK_SD_EN_OUT_OFF 0b00010000
385 #define MASK_SD_SM_2 0b00000010
386 #define SHIFT_SD_EN_FRAC0 5
387 #define SHIFT_SD_EN_OUT_OFF 4
388 #define SHIFT_SD_SM_2 0
390 #define MASK_CP_HIZ 0b00000011
391 #define SHIFT_CP_HIZ 0
393 #define MASK_EN_PFD_CP 0b10000000
394 #define MASK_BLEED_POL 0b01000000
395 #define MASK_INT_ABP 0b00000100
396 #define MASK_BLEED_EN 0b00000001
397 #define SHIFT_EN_PFD_CP 7
398 #define SHIFT_BLEED_POL 6
399 #define SHIFT_INT_ABP 2
400 #define SHIFT_BLEED_EN_ 0
402 #define MASK_CP_CURRENT 0b00001111
403 #define SHIFT_CP_CURRENT 0
405 #define MASK_BICP 0b11111111
408 #define MASK_FRAC27_0 0b11111111
409 #define SHIFT_FRAC27_0 0
411 #define MASK_FRAC213_8 0b00111111
412 #define SHIFT_FRAC213_8 0
414 #define MASK_PHASE_ADJ_EN 0b00000010
415 #define SHIFT_PHASE_ADJ_EN 1
417 #define MASK_SI_VCO_FORCE_CAPSVCOI 0b00010000
418 #define MASK_SI_VCO_FORCE_VCO 0b00000010
419 #define MASK_SI_VCO_FORCE_CAPS 0b00000001
420 #define SHIFT_SI_VCO_FORCE_CAPSVCOI 4
421 #define SHIFT_SI_VCO_FORCE_VCO 1
422 #define SHIFT_SI_VCO_FORCE_CAPS 0
424 #define MASK_LOCK_DETECT 0b00000001
425 #define SHIFT_LOCK_DETECT 0
427 #define MASK_SPI_1P8_3P3_CTRL 0b00010000
428 #define SHIFT_SPI_1P8_3P3_CTRL 4
430 #define MASK_EN_BIAS_R 0b10000000
431 #define MASK_REFBUF_EN 0b00100000
432 #define SHIFT_EN_BIAS_R 7
433 #define SHIFT_REFBUF_EN 5
435 #define MASK_MIX_OE 0b10000000
436 #define MASK_LO_OE 0b01000000
437 #define MASK_USEEXT_LOI 0b00100000
438 #define MASK_OUT_DIVRATIO 0b00011111
439 #define SHIFT_MIX_OE 7
440 #define SHIFT_LO_OE 6
441 #define SHIFT_USEEXT_LOI 5
442 #define SHIFT_OUT_DIVRATIO 0
444 #define MASK_FRAC2_SLV7_0 0b11111111
445 #define SHIFT_FRAC2_SLV7_0 0
447 #define MASK_FRAC2_SLV13_8 0b00111111
448 #define SHIFT_FRAC2_SLV13_8 0
450 #define MASK_FRAC_SLV7_0 0b11111111
451 #define SHIFT_FRAC_SLV7_0 0
453 #define MASK_FRAC_SLV15_8 0b11111111
454 #define SHIFT_FRAC_SLV15_8 0
456 #define MASK_FRAC_SLV23_16 0b11111111
457 #define SHIFT_FRAC_SLV23_16 0
459 #define MASK_PHASE_SLV7_0 0b11111111
460 #define SHIFT_PHASE_SLV7_0 0
462 #define MASK_PHASE_SLV15_8 0b11111111
463 #define SHIFT_PHASE_SLV15_8 0
465 #define MASK_PHASE_SLV23_16 0b11111111
466 #define SHIFT_PHASE_SLV23_16 0
468 #define MASK_INT_DIV7_0 0b11111111
469 #define SHIFT_INT_DIV7_0 0
471 #define MASK_INT_DIV15_8 0b11111111
472 #define SHIFT_INT_DIV15_8 0
474 #define MASK_R_DIV_SLV 0b01111111
475 #define SHIFT_R_DIV_SLV 0
477 #define MASK_RDIV2_SEL_SLV 0b00000001
478 #define SHIFT_RDIV2_SEL_SLV 0
480 #define MASK_DSM_LAUNCH_DLY 0b00011000
481 #define MASK_DISABLE_FREQHOP 0b00000100
482 #define MASK_DISABLE_DBLBUFFERING 0b00000010
483 #define MASK_DISABLE_PHASEADJ 0b00000001
484 #define SHIFT_DSM_LAUNCH_DLY 3
485 #define SHIFT_DISABLE_FREQHOP 2
486 #define SHIFT_DISABLE_DBLBUFFERING 1
487 #define SHIFT_DISABLE_PHASEADJ 0
489 #endif // !ADRF6660_MAP_H
@ MULTI_FUNC_SYNTH_CTL_0235_ADDR
@ MULTI_FUNC_SYNTH_CTL_022C_ADDR
@ DVGA_TRIM2_HP5V_OVERRIDE_ADDR
@ ATTEN_READBACK_CH2_ADDR
@ DVGA_TRIM1_HP5V_OVERRIDE_ADDR
@ DVGA_TRIM1_HP3V_OVERRIDE_ADDR
@ MULTI_FUNC_SYNTH_CTL_0214_ADDR
@ MULTI_FUNC_SYNTH_CTL_022D_ADDR
@ DVGA_TRIM2_LP5V_OVERRIDE_ADDR
@ DVGA_TRIM_READBACK_CH1_ADDR
@ ATTEN_READBACK_CH1_ADDR
@ DVGA_TRIM_READBACK_CH2_ADDR
@ DVGA_TRIM1_LP3V_OVERRIDE_ADDR
@ DVGA_TRIM2_HP3V_OVERRIDE_ADDR
@ DVGA_TRIM1_LP5V_OVERRIDE_ADDR
@ DVGA_TRIM2_LP3V_OVERRIDE_ADDR