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ADRF6650_Map.h
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1 /** \file ADRF6650_Map.h
2 * \brief <a href="https://www.inmechasol.org/" target="_blank">IMS</a>:
3  <a href="https://github.com/InMechaSol/ccNOos" target="_blank">ccNOos</a>,
4  Declarations for straight C and C++
5 
6  Copyright 2021 <a href="https://www.inmechasol.org/" target="_blank">InMechaSol, Inc</a>
7 
8  Licensed under the Apache License, Version 2.0(the "License");
9  you may not use this file except in compliance with the License.
10  You may obtain a copy of the License at
11 
12  http://www.apache.org/licenses/LICENSE-2.0
13 
14  Unless required by applicable law or agreed to in writing, software
15  distributed under the License is distributed on an "AS IS" BASIS,
16  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
17  See the License for the specific language governing permissions and
18  limitations under the License.
19 
20 Notes:
21  (.c includes .h) - for straight C or
22  (.cpp includes .c which includes .h) - for C++ wrapped straight C
23  *Always compiled to a single compilation unit, either C or CPP, not both
24 
25 */
26 
27 #ifndef ADRF6660_MAP_H
28 #define ADRF6660_MAP_H
29 
30 typedef enum {
34  CHIP_TYPE_ADDR = 0x0003,
37  SCRATCH_ADDR = 0x000A,
38  SPI_REVISON_ADDR = 0x000B,
39  VENDOR_ID_L_ADDR = 0x000C,
40  VENDOR_ID_H_ADDR = 0x000D,
46  TDD_BYPASS_ADDR = 0x0100,
47  CONFIG_ADDR = 0x0101,
48  EN_MASK_ADDR = 0x0102,
49  DVGA_MODE_ADDR = 0x0103,
50  DVGA_GAIN1_ADDR = 0x0104,
51  DVGA_GAIN2_ADDR = 0x0105,
67  GPO1_SELECT_ADDR = 0x1033,
69  INT_L_ADDR = 0x1200,
70  INT_H_ADDR = 0x1201,
71  FRAC1_L_ADDR = 0x1202,
72  FRAC1_M_ADDR = 0x1203,
73  FRAC1_H_ADDR = 0x1204,
77  MOD_L_ADDR = 0x1208,
78  MOD_H_ADDR = 0x1209,
79  SYNTH_ADDR = 0x120B,
80  R_DIV_ADDR = 0x120C,
81  SYNTH_0_ADDR = 0x120E,
83  SI_VCO_SEL_ADDR = 0x1217,
84  VCO_FSM_ADDR = 0x121F,
85  SD_CTRL_ADDR = 0x122A,
88  CP_CURR_ADDR = 0x122E,
89  BICP_ADDR = 0x122F,
90  FRAC2_L_ADDR = 0x1233,
91  FRAC2_H_ADDR = 0x1234,
94  LOCK_DETECT_ADDR = 0x124D,
96  LO_CNTRL2_ADDR = 0x140E,
97  LO_CNTRL8_ADDR = 0x1414,
112 
113 // Register bit definitions
114 //#define ADI_SPI_CONFIG_ADDR 0x0000
115 #define MASK_SOFTRESET_ 0b10000000
116 #define MASK_LSB_FIRST_ 0b01000000
117 #define MASK_ENDIAN_ 0b00100000
118 #define MASK_SDOACTIVE_ 0b00010000
119 #define MASK_SDOACTIVE 0b00001000
120 #define MASK_ENDIAN 0b00000100
121 #define MASK_LSB_FIRST 0b00000010
122 #define MASK_SOFTRESET 0b00000001
123 #define SHIFT_SOFTRESET_ 7
124 #define SHIFT_LSB_FIRST_ 6
125 #define SHIFT_ENDIAN_ 5
126 #define SHIFT_SDOACTIVE_ 4
127 #define SHIFT_SDOACTIVE 3
128 #define SHIFT_ENDIAN 2
129 #define SHIFT_LSB_FIRST 1
130 #define SHIFT_SOFTRESET 0
131 //#define SPI_CONFIG_B_ADDR 0x0001
132 #define MASK_SINGLE_INSTRUCTION 0b10000000
133 #define MASK_CSB_STALL 0b01000000
134 #define MASK_MASTER_SLAVE_RB 0b00100000
135 #define MASK_SOFTRESET_B 0b00000110
136 #define MASK_MASTER_SLAVE_TRANSFER 0b00000001
137 #define SHIFT_SINGLE_INSTRUCTION 7
138 #define SHIFT_CSB_STALL 6
139 #define SHIFT_MASTER_SLAVE_RB 5
140 #define SHIFT_SOFTRESET_B 1
141 #define SHIFT_MASTER_SLAVE_TRANSFER 0
142 //#define DEVICE_CONFIG_ADDR 0x0002
143 #define MASK_OPERATING_MODE 0b00001100
144 #define MASK_POWER_MODE 0b00000011
145 #define SHIFT_OPERATING_MODE 2
146 #define SHIFT_POWER_MODE 0
147 //#define CHIP_TYPE_ADDR 0x0003
148 #define MASK_CHIPTYPE 0b11111111
149 #define SHIFT_CHIPTYPE 0
150 //#define PRODUCT_ID_1_ADDR 0x0004
151 #define MASK_PRODUCT_ID_1 0b11111111
152 #define SHIFT_PRODUCT_ID_1 0
153 //#define PRODUCT_ID_2_ADDR 0x0005
154 #define MASK_PRODUCT_ID_2 0b11111111
155 #define SHIFT_PRODUCT_ID_2 0
156 //#define SCRATCH_ADDR 0x000A
157 #define MASK_SCRATCHPAD 0b11111111
158 #define SHIFT_SCRATCHPAD 0
159 //#define SPI_REVISON_ADDR 0x000B
160 #define MASK_SPI_VER 0b11111111
161 #define SHIFT_SPI_VER 0
162 //#define VENDOR_ID_L_ADDR 0x000C
163 #define MASK_VENDOR_ID7_0 0b11111111
164 #define SHIFT_VENDOR_ID7_0 0
165 //#define VENDOR_ID_H_ADDR 0x000D
166 #define MASK_VENDOR_ID15_8 0b11111111
167 #define SHIFT_VENDOR_ID15_8 0
168 //#define BLOCK_RESETS_A_ADDR 0x0021
169 #define MASK_DVGA_CH2_RSTB 0b00000010
170 #define MASK_DVGA_CH1_RSTB 0b00000001
171 #define SHIFT_DVGA_CH2_RSTB 1
172 #define SHIFT_DVGA_CH1_RSTB 0
173 //#define ATTEN_READBACK_CH1_ADDR 0x003C
174 #define MASK_ATTEN_READBACK_CH1 0b11111111
175 #define SHIFT_ATTEN_READBACK_CH1 0
176 //#define ATTEN_READBACK_CH2_ADDR 0x003D
177 #define MASK_ATTEN_READBACK_CH2 0b11111111
178 #define SHIFT_ATTEN_READBACK_CH2 0
179 //#define DVGA_TRIM_READBACK_CH1_ADDR 0x003E
180 #define MASK_DVGA_TRIM_READBACK_CH1 0b11111111
181 #define SHIFT_DVGA_TRIM_READBACK_CH1 0
182 //#define DVGA_TRIM_READBACK_CH2_ADDR 0x003F
183 #define MASK_DVGA_TRIM_READBACK_CH2 0b11111111
184 #define SHIFT_DVGA_TRIM_READBACK_CH2 0
185 //#define TDD_BYPASS_ADDR 0x0100
186 #define MASK_DVGA_ENB_CH2 0b10000000
187 #define MASK_DVGA_ENB_CH1 0b01000000
188 #define MASK_IF_ENB_CH2 0b00100000
189 #define MASK_IF_ENB_CH1 0b00010000
190 #define MASK_LO_STG23_ENB_CH2 0b00001000
191 #define MASK_LO_STG23_ENB_CH1 0b00000100
192 #define MASK_LO_STG1_ENB 0b00000010
193 #define MASK_BYPASS_TDD 0b00000001
194 #define SHIFT_DVGA_ENB_CH2 7
195 #define SHIFT_DVGA_ENB_CH1 6
196 #define SHIFT_IF_ENB_CH2 5
197 #define SHIFT_IF_ENB_CH1 4
198 #define SHIFT_LO_STG23_ENB_CH2 3
199 #define SHIFT_LO_STG23_ENB_CH1 2
200 #define SHIFT_LO_STG1_ENB 1
201 #define SHIFT_BYPASS_TDD 0
202 //#define CONFIG_ADDR 0x0101
203 #define MASK_IFLIN_BIAS_EN 0b00100000
204 #define MASK_IFMAIN_BIAS_EN 0b00010000
205 #define MASK_SPI_18_33_SEL 0b00000001
206 #define SHIFT_IFLIN_BIAS_EN 5
207 #define SHIFT_IFMAIN_BIAS_EN 4
208 #define SHIFT_SPI_18_33_SEL 0
209 //#define EN_MASK_ADDR 0x0102
210 #define MASK_PLL_ENB_CH12_MASK 0b10000000
211 #define MASK_DVGA_ENB_CH2_MASK 0b01000000
212 #define MASK_DVGA_ENB_CH1_MASK 0b00100000
213 #define MASK_IF_ENB_CH2_MASK 0b00010000
214 #define MASK_IF_ENB_CH1_MASK 0b00001000
215 #define MASK_LO_STG23_ENB_CH2_MASK 0b00000100
216 #define MASK_LO_STG23_ENB_CH1_MASK 0b00000010
217 #define MASK_LO_STG1_ENB_MASK 0b00000001
218 #define SHIFT_PLL_ENB_CH12_MASK 7
219 #define SHIFT_DVGA_ENB_CH2_MASK 6
220 #define SHIFT_DVGA_ENB_CH1_MASK 5
221 #define SHIFT_IF_ENB_CH2_MASK 4
222 #define SHIFT_IF_ENB_CH1_MASK 3
223 #define SHIFT_LO_STG23_ENB_CH2_MASK 2
224 #define SHIFT_LO_STG23_ENB_CH1_MASK 1
225 #define SHIFT_LO_STG1_ENB_MASK 0
226 //#define DVGA_MODE_ADDR 0x0103
227 #define MASK_DVGA_5V_SEL 0b10000000
228 #define MASK_DVGA_FA_STEP 0b01100000
229 #define MASK_DVGA_UPDN_STEP 0b00011000
230 #define MASK_DVGA_GAIN_MODE 0b00000111
231 #define SHIFT_DVGA_5V_SEL 7
232 #define SHIFT_DVGA_FA_STEP 5
233 #define SHIFT_DVGA_UPDN_STEP 3
234 #define SHIFT_DVGA_GAIN_MODE 0
235 //#define DVGA_GAIN1_ADDR 0x0104
236 #define MASK_DVGA_HP_SEL 0b01000000
237 #define MASK_DVGA_GAIN_CH1 0b00111111
238 #define SHIFT_DVGA_HP_SEL 6
239 #define SHIFT_DVGA_GAIN_CH1 0
240 //#define DVGA_GAIN2_ADDR 0x0105
241 #define MASK_DVGA_GAIN_CH2 0b00111111
242 #define SHIFT_DVGA_GAIN_CH2 0
243 //#define LPF_OVERRIDE_ADDR 0x0300
244 #define MASK_LPF2_OVERRIDE 0b01110000
245 #define MASK_LPF1_OVERRIDE 0b00001110
246 #define MASK_LPF_DPLX_EN_OVERRIDE 0b00000001
247 #define SHIFT_LPF2_OVERRIDE 4
248 #define SHIFT_LPF1_OVERRIDE 1
249 #define SHIFT_LPF_DPLX_EN_OVERRIDE 0
250 //#define IFMAIN_OVERRIDE_ADDR 0x0301
251 #define MASK_IFMAIN_BIAS_OVERRIDE 0b00001111
252 #define SHIFT_IFMAIN_BIAS_OVERRIDE 0
253 //#define IFLIN_OVERRIDE_ADDR 0x0302
254 #define MASK_IFLIN_BIAS_OVERRIDE 0b00001111
255 #define SHIFT_IFLIN_BIAS_OVERRIDE 0
256 //#define VGS_OVERRIDE_ADDR 0x0303
257 #define MASK_VGS_OVERRIDE 0b00001111
258 #define SHIFT_VGS_OVERRIDE 0
259 //#define DVGA_TRIM1_LP3V_OVERRIDE_ADDR 0x0304
260 #define MASK_DVGA_TRIM_LP_3V_CH1_OVERRIDE 0b00011111
261 #define SHIFTDVGA_TRIM_LP_3V_CH1_OVERRIDE 0
262 //#define DVGA_TRIM1_HP3V_OVERRIDE_ADDR 0x0305
263 #define MASK_DVGA_TRIM_HP_3V_CH1_OVERRIDE 0b00011111
264 #define SHIFTDVGA_TRIM_HP_3V_CH1_OVERRIDE 0
265 //#define DVGA_TRIM1_LP5V_OVERRIDE_ADDR 0x0306
266 #define MASK_DVGA_TRIM_LP_5V_CH1_OVERRIDE 0b00011111
267 #define SHIFTDVGA_TRIM_LP_5V_CH1_OVERRIDE 0
268 //#define DVGA_TRIM1_HP5V_OVERRIDE_ADDR 0x0307
269 #define MASK_DVGA_TRIM_HP_5V_CH1_OVERRIDE 0b00011111
270 #define SHIFTDVGA_TRIM_HP_5V_CH1_OVERRIDE 0
271 //#define DVGA_TRIM2_LP3V_OVERRIDE_ADDR 0x0308
272 #define MASK_DVGA_TRIM_LP_3V_CH2_OVERRIDE 0b00011111
273 #define SHIFTDVGA_TRIM_LP_3V_CH2_OVERRIDE 0
274 //#define DVGA_TRIM2_HP3V_OVERRIDE_ADDR 0x0309
275 #define MASK_DVGA_TRIM_HP_3V_CH2_OVERRIDE 0b00011111
276 #define SHIFTDVGA_TRIM_HP_3V_CH2_OVERRIDE 0
277 //#define DVGA_TRIM2_LP5V_OVERRIDE_ADDR 0x030A
278 #define MASK_DVGA_TRIM_LP_5V_CH2_OVERRIDE 0b00011111
279 #define SHIFTDVGA_TRIM_LP_5V_CH2_OVERRIDE 0
280 //#define DVGA_TRIM2_HP5V_OVERRIDE_ADDR 0x030B
281 #define MASK_DVGA_TRIM_HP_5V_CH2_OVERRIDE 0b00011111
282 #define SHIFTDVGA_TRIM_HP_5V_CH2_OVERRIDE 0
283 //#define OVERRIDE_SELECT_ADDR 0x0310
284 #define MASK_SPARE2_OVERRIDE_SEL 0b10000000
285 #define MASK_SPARE1_OVERRIDE_SEL 0b01000000
286 #define MASK_DVGA_TRIM_CH2_OVERRIDE_SEL 0b00100000
287 #define MASK_DVGA_TRIM_CH1_OVERRIDE_SEL 0b00010000
288 #define MASK_VGS_OVERRIDE_SEL 0b00001000
289 #define MASK_IFLIN_TRIM_OVERRIDE_SEL 0b00000100
290 #define MASK_IFMAIN_TRIM_OVERRIDE_SEL 0b00000010
291 #define MASK_LPF_TRIM_OVERRIDE_SEL 0b00000001
292 #define SHIFT_SPARE2_OVERRIDE_SEL 7
293 #define SHIFT_SPARE1_OVERRIDE_SEL 6
294 #define SHIFT_DVGA_TRIM_CH2_OVERRIDE_SEL 5
295 #define SHIFT_DVGA_TRIM_CH1_OVERRIDE_SEL 4
296 #define SHIFT_VGS_OVERRIDE_SEL 3
297 #define SHIFT_IFLIN_TRIM_OVERRIDE_SEL 2
298 #define SHIFT_IFMAIN_TRIM_OVERRIDE_SEL 1
299 #define SHIFT_LPF_TRIM_OVERRIDE_SEL 0
300 //#define BLOCK_RESETS_ADDR 0x1021
301 #define MASK_ARSTB_BLOCK_LKD 0b01000000
302 #define MASK_ARSTB_BLOCK_AUTOCAL 0b00100000
303 #define MASK_ARSTB_BLOCK_NDIV 0b00010000
304 #define MASK_ARSTB_BLOCK_RDIV 0b00001000
305 #define MASK_ARSTB_BLOCK_DSMOSTG 0b00000100
306 #define MASK_ARSTB_BLOCK_DSMCORE 0b00000010
307 #define MASK_ARSTB_BLOCK_DSMALL 0b00000001
308 #define SHIFT_ARSTB_BLOCK_LKD 6
309 #define SHIFT_ARSTB_BLOCK_AUTOCAL 5
310 #define SHIFT_ARSTB_BLOCK_NDIV 4
311 #define SHIFT_ARSTB_BLOCK_RDIV 3
312 #define SHIFT_ARSTB_BLOCK_DSMOSTG 2
313 #define SHIFT_ARSTB_BLOCK_DSMCORE 1
314 #define SHIFT_ARSTB_BLOCK_DSMALL 0
315 //#define GPO1_CONTROL_ADDR 0x1032
316 #define MASK_GPO1_BLK_SEL 0b01111000
317 #define MASK_GPO1_ENABLE 0b00000001
318 #define SHIFT__GPO1_BLK_SEL 3
319 #define SHIFT__GPO1_ENABLE 0
320 //#define GPO1_SELECT_ADDR 0x1033
321 #define MASK_GPO1_SGNL_SEL 0b11111111
322 #define SHIFT_GPO1_SGNL_SEL 0
323 //#define SIG_PATH_9_NORMAL_ADDR 0x1109
324 #define MASK_TRM_MIXLODRV_DRV_POUT 0b00011000
325 #define MASK_TRM_XLODRV_DRV_POUT 0b00000110
326 #define SHIFT_TRM_MIXLODRV_DRV_POUT 3
327 #define SHIFT_TRM_XLODRV_DRV_POUT 1
328 //#define INT_L_ADDR 0x1200
329 #define MASK_INT_DIV7_0 0b11111111
330 #define SHIFT_INT_DIV7_0 0
331 //#define INT_H_ADDR 0x1201
332 #define MASK_INT_DIV15_8 0b11111111
333 #define SHIFT_INT_DIV15_8 0
334 //#define FRAC1_L_ADDR 0x1202
335 #define MASK_FRAC7_0 0b11111111
336 #define SHIFT_FRAC7_0 0
337 //#define FRAC1_M_ADDR 0x1203
338 #define MASK_FRAC15_8 0b11111111
339 #define SHIFT_FRAC15_8 0
340 //#define FRAC1_H_ADDR 0x1204
341 #define MASK_FRAC23_16 0b11111111
342 #define SHIFT_FRAC23_16 0
343 //#define SD_PHASE_L_0_ADDR 0x1205
344 #define MASK_PHASE7_0 0b11111111
345 #define SHIFT_PHASE7_0 0
346 //#define SD_PHASE_M_0_ADDR 0x1206
347 #define MASK_PHASE15_8 0b11111111
348 #define SHIFT_PHASE15_8 0
349 //#define SD_PHASE_H_0_ADDR 0x1207
350 #define MASK_PHASE23_16 0b11111111
351 #define SHIFT_PHASE23_16 0
352 //#define MOD_L_ADDR 0x1208
353 #define MASK_MOD7_0 0b11111111
354 #define SHIFT_MOD7_0 0
355 //#define MOD_H_ADDR 0x1209
356 #define MASK_MOD13_8 0b00111111
357 #define SHIFT_MOD13_8 0
358 //#define SYNTH_ADDR 0x120B
359 #define MASK_PRE_SEL 0b00000010
360 #define MASK_EN_FBDIV 0b00000001
361 #define SHIFT_PRE_SEL 1
362 #define SHIFT_EN_FBDIV 0
363 //#define R_DIV_ADDR 0x120C
364 #define MASK_R_DIV 0b01111111
365 #define SHIFT_R_DIV 0
366 //#define SYNTH_0_ADDR 0x120E
367 #define MASK_DOUBLER_EN 0b00001000
368 #define MASK_RDIV2_SEL 0b00000001
369 #define SHIFT_DOUBLER_EN 3
370 #define SHIFT_RDIV2_SEL 0
371 //#define MULTI_FUNC_SYNTH_CTL_0214_ADDR 0x1214
372 #define MASK_LD_BIAS 0b11000000
373 #define MASK_LDP 0b00111000
374 #define SHIFT_LD_BIAS 6
375 #define SHIFT_LDP 3
376 //#define SI_VCO_SEL_ADDR 0x1217
377 #define MASK_SI_VCO_SEL 0b00001111
378 #define SHIFT_SI_VCO_SEL 0
379 //#define VCO_FSM_ADDR 0x121F
380 #define MASK_DISABLE_CAL 0b01000000
381 #define SHIFT_DISABLE_CAL 6
382 //#define SD_CTRL_ADDR 0x122A
383 #define MASK_SD_EN_FRAC0 0b00100000
384 #define MASK_SD_EN_OUT_OFF 0b00010000
385 #define MASK_SD_SM_2 0b00000010
386 #define SHIFT_SD_EN_FRAC0 5
387 #define SHIFT_SD_EN_OUT_OFF 4
388 #define SHIFT_SD_SM_2 0
389 //#define MULTI_FUNC_SYNTH_CTL_022C_ADDR 0x122C
390 #define MASK_CP_HIZ 0b00000011
391 #define SHIFT_CP_HIZ 0
392 //#define MULTI_FUNC_SYNTH_CTL_022D_ADDR 0x122D
393 #define MASK_EN_PFD_CP 0b10000000
394 #define MASK_BLEED_POL 0b01000000
395 #define MASK_INT_ABP 0b00000100
396 #define MASK_BLEED_EN 0b00000001
397 #define SHIFT_EN_PFD_CP 7
398 #define SHIFT_BLEED_POL 6
399 #define SHIFT_INT_ABP 2
400 #define SHIFT_BLEED_EN_ 0
401 //#define CP_CURR_ADDR 0x122E
402 #define MASK_CP_CURRENT 0b00001111
403 #define SHIFT_CP_CURRENT 0
404 //#define BICP_ADDR 0x122F
405 #define MASK_BICP 0b11111111
406 #define SHIFT_BICP 0
407 //#define FRAC2_L_ADDR 0x1233
408 #define MASK_FRAC27_0 0b11111111
409 #define SHIFT_FRAC27_0 0
410 //#define FRAC2_H_ADDR 0x1234
411 #define MASK_FRAC213_8 0b00111111
412 #define SHIFT_FRAC213_8 0
413 //#define MULTI_FUNC_SYNTH_CTL_0235_ADDR 0x1235
414 #define MASK_PHASE_ADJ_EN 0b00000010
415 #define SHIFT_PHASE_ADJ_EN 1
416 //#define VCO_LUT_CTRL_ADDR 0x1240
417 #define MASK_SI_VCO_FORCE_CAPSVCOI 0b00010000
418 #define MASK_SI_VCO_FORCE_VCO 0b00000010
419 #define MASK_SI_VCO_FORCE_CAPS 0b00000001
420 #define SHIFT_SI_VCO_FORCE_CAPSVCOI 4
421 #define SHIFT_SI_VCO_FORCE_VCO 1
422 #define SHIFT_SI_VCO_FORCE_CAPS 0
423 //#define LOCK_DETECT_ADDR 0x124D
424 #define MASK_LOCK_DETECT 0b00000001
425 #define SHIFT_LOCK_DETECT 0
426 //#define MULTI_FUNC_CTRL_ADDR 0x1401
427 #define MASK_SPI_1P8_3P3_CTRL 0b00010000
428 #define SHIFT_SPI_1P8_3P3_CTRL 4
429 //#define LO_CNTRL2_ADDR 0x140E
430 #define MASK_EN_BIAS_R 0b10000000
431 #define MASK_REFBUF_EN 0b00100000
432 #define SHIFT_EN_BIAS_R 7
433 #define SHIFT_REFBUF_EN 5
434 //#define LO_CNTRL8_ADDR 0x1414
435 #define MASK_MIX_OE 0b10000000
436 #define MASK_LO_OE 0b01000000
437 #define MASK_USEEXT_LOI 0b00100000
438 #define MASK_OUT_DIVRATIO 0b00011111
439 #define SHIFT_MIX_OE 7
440 #define SHIFT_LO_OE 6
441 #define SHIFT_USEEXT_LOI 5
442 #define SHIFT_OUT_DIVRATIO 0
443 //#define FRAC2_L_SLAVE_ADDR 0x1541
444 #define MASK_FRAC2_SLV7_0 0b11111111
445 #define SHIFT_FRAC2_SLV7_0 0
446 //#define FRAC2_H_SLAVE_ADDR 0x1542
447 #define MASK_FRAC2_SLV13_8 0b00111111
448 #define SHIFT_FRAC2_SLV13_8 0
449 //#define FRAC_L_SLAVE_ADDR 0x1543
450 #define MASK_FRAC_SLV7_0 0b11111111
451 #define SHIFT_FRAC_SLV7_0 0
452 //#define FRAC_M_SLAVE_ADDR 0x1544
453 #define MASK_FRAC_SLV15_8 0b11111111
454 #define SHIFT_FRAC_SLV15_8 0
455 //#define FRAC_H_SLAVE2_ADDR 0x1545
456 #define MASK_FRAC_SLV23_16 0b11111111
457 #define SHIFT_FRAC_SLV23_16 0
458 //#define PHASE_L_SLAVE_ADDR 0x1546
459 #define MASK_PHASE_SLV7_0 0b11111111
460 #define SHIFT_PHASE_SLV7_0 0
461 //#define PHASE_M_SLAVE_ADDR 0x1547
462 #define MASK_PHASE_SLV15_8 0b11111111
463 #define SHIFT_PHASE_SLV15_8 0
464 //#define PHASE_H_SLAVE_ADDR 0x1548
465 #define MASK_PHASE_SLV23_16 0b11111111
466 #define SHIFT_PHASE_SLV23_16 0
467 //#define INT_DIV_L_SLAVE_ADDR 0x1549
468 #define MASK_INT_DIV7_0 0b11111111
469 #define SHIFT_INT_DIV7_0 0
470 //#define INT_DIV_H_SLAVE_ADDR 0x154A
471 #define MASK_INT_DIV15_8 0b11111111
472 #define SHIFT_INT_DIV15_8 0
473 //#define R_DIV_SLAVE_ADDR 0x154B
474 #define MASK_R_DIV_SLV 0b01111111
475 #define SHIFT_R_DIV_SLV 0
476 //#define RDIV2_SEL_SLAVE_ADDR 0x154C
477 #define MASK_RDIV2_SEL_SLV 0b00000001
478 #define SHIFT_RDIV2_SEL_SLV 0
479 //#define DISABLE_CFG_ADDR 0x1583
480 #define MASK_DSM_LAUNCH_DLY 0b00011000
481 #define MASK_DISABLE_FREQHOP 0b00000100
482 #define MASK_DISABLE_DBLBUFFERING 0b00000010
483 #define MASK_DISABLE_PHASEADJ 0b00000001
484 #define SHIFT_DSM_LAUNCH_DLY 3
485 #define SHIFT_DISABLE_FREQHOP 2
486 #define SHIFT_DISABLE_DBLBUFFERING 1
487 #define SHIFT_DISABLE_PHASEADJ 0
488 
489 #endif // !ADRF6660_MAP_H
SPI_CONFIG_B_ADDR
@ SPI_CONFIG_B_ADDR
Definition: ADRF6650_Map.h:32
EN_MASK_ADDR
@ EN_MASK_ADDR
Definition: ADRF6650_Map.h:48
MULTI_FUNC_SYNTH_CTL_0235_ADDR
@ MULTI_FUNC_SYNTH_CTL_0235_ADDR
Definition: ADRF6650_Map.h:92
SYNTH_0_ADDR
@ SYNTH_0_ADDR
Definition: ADRF6650_Map.h:81
PHASE_L_SLAVE_ADDR
@ PHASE_L_SLAVE_ADDR
Definition: ADRF6650_Map.h:103
SD_CTRL_ADDR
@ SD_CTRL_ADDR
Definition: ADRF6650_Map.h:85
MULTI_FUNC_SYNTH_CTL_022C_ADDR
@ MULTI_FUNC_SYNTH_CTL_022C_ADDR
Definition: ADRF6650_Map.h:86
PRODUCT_ID_2_ADDR
@ PRODUCT_ID_2_ADDR
Definition: ADRF6650_Map.h:36
PRODUCT_ID_1_ADDR
@ PRODUCT_ID_1_ADDR
Definition: ADRF6650_Map.h:35
DEVICE_CONFIG_ADDR
@ DEVICE_CONFIG_ADDR
Definition: ADRF6650_Map.h:33
DVGA_TRIM2_HP5V_OVERRIDE_ADDR
@ DVGA_TRIM2_HP5V_OVERRIDE_ADDR
Definition: ADRF6650_Map.h:63
MULTI_FUNC_CTRL_ADDR
@ MULTI_FUNC_CTRL_ADDR
Definition: ADRF6650_Map.h:95
INT_L_ADDR
@ INT_L_ADDR
Definition: ADRF6650_Map.h:69
SD_PHASE_H_0_ADDR
@ SD_PHASE_H_0_ADDR
Definition: ADRF6650_Map.h:76
LO_CNTRL2_ADDR
@ LO_CNTRL2_ADDR
Definition: ADRF6650_Map.h:96
FRAC2_H_SLAVE_ADDR
@ FRAC2_H_SLAVE_ADDR
Definition: ADRF6650_Map.h:99
INT_DIV_H_SLAVE_ADDR
@ INT_DIV_H_SLAVE_ADDR
Definition: ADRF6650_Map.h:107
SYNTH_ADDR
@ SYNTH_ADDR
Definition: ADRF6650_Map.h:79
DISABLE_CFG_ADDR
@ DISABLE_CFG_ADDR
Definition: ADRF6650_Map.h:110
FRAC2_H_ADDR
@ FRAC2_H_ADDR
Definition: ADRF6650_Map.h:91
VGS_OVERRIDE_ADDR
@ VGS_OVERRIDE_ADDR
Definition: ADRF6650_Map.h:55
DVGA_GAIN1_ADDR
@ DVGA_GAIN1_ADDR
Definition: ADRF6650_Map.h:50
ATTEN_READBACK_CH2_ADDR
@ ATTEN_READBACK_CH2_ADDR
Definition: ADRF6650_Map.h:43
DVGA_TRIM1_HP5V_OVERRIDE_ADDR
@ DVGA_TRIM1_HP5V_OVERRIDE_ADDR
Definition: ADRF6650_Map.h:59
OVERRIDE_SELECT_ADDR
@ OVERRIDE_SELECT_ADDR
Definition: ADRF6650_Map.h:64
VCO_LUT_CTRL_ADDR
@ VCO_LUT_CTRL_ADDR
Definition: ADRF6650_Map.h:93
DVGA_TRIM1_HP3V_OVERRIDE_ADDR
@ DVGA_TRIM1_HP3V_OVERRIDE_ADDR
Definition: ADRF6650_Map.h:57
FRAC1_L_ADDR
@ FRAC1_L_ADDR
Definition: ADRF6650_Map.h:71
R_DIV_ADDR
@ R_DIV_ADDR
Definition: ADRF6650_Map.h:80
LPF_OVERRIDE_ADDR
@ LPF_OVERRIDE_ADDR
Definition: ADRF6650_Map.h:52
GPO1_SELECT_ADDR
@ GPO1_SELECT_ADDR
Definition: ADRF6650_Map.h:67
FRAC2_L_ADDR
@ FRAC2_L_ADDR
Definition: ADRF6650_Map.h:90
SCRATCH_ADDR
@ SCRATCH_ADDR
Definition: ADRF6650_Map.h:37
MULTI_FUNC_SYNTH_CTL_0214_ADDR
@ MULTI_FUNC_SYNTH_CTL_0214_ADDR
Definition: ADRF6650_Map.h:82
MULTI_FUNC_SYNTH_CTL_022D_ADDR
@ MULTI_FUNC_SYNTH_CTL_022D_ADDR
Definition: ADRF6650_Map.h:87
DVGA_TRIM2_LP5V_OVERRIDE_ADDR
@ DVGA_TRIM2_LP5V_OVERRIDE_ADDR
Definition: ADRF6650_Map.h:62
VCO_FSM_ADDR
@ VCO_FSM_ADDR
Definition: ADRF6650_Map.h:84
IFMAIN_OVERRIDE_ADDR
@ IFMAIN_OVERRIDE_ADDR
Definition: ADRF6650_Map.h:53
LO_CNTRL8_ADDR
@ LO_CNTRL8_ADDR
Definition: ADRF6650_Map.h:97
PHASE_H_SLAVE_ADDR
@ PHASE_H_SLAVE_ADDR
Definition: ADRF6650_Map.h:105
INT_H_ADDR
@ INT_H_ADDR
Definition: ADRF6650_Map.h:70
VENDOR_ID_H_ADDR
@ VENDOR_ID_H_ADDR
Definition: ADRF6650_Map.h:40
SPI_REVISON_ADDR
@ SPI_REVISON_ADDR
Definition: ADRF6650_Map.h:38
FRAC_M_SLAVE_ADDR
@ FRAC_M_SLAVE_ADDR
Definition: ADRF6650_Map.h:101
SD_PHASE_M_0_ADDR
@ SD_PHASE_M_0_ADDR
Definition: ADRF6650_Map.h:75
VENDOR_ID_L_ADDR
@ VENDOR_ID_L_ADDR
Definition: ADRF6650_Map.h:39
LOCK_DETECT_ADDR
@ LOCK_DETECT_ADDR
Definition: ADRF6650_Map.h:94
FRAC_H_SLAVE2_ADDR
@ FRAC_H_SLAVE2_ADDR
Definition: ADRF6650_Map.h:102
CONFIG_ADDR
@ CONFIG_ADDR
Definition: ADRF6650_Map.h:47
DVGA_TRIM_READBACK_CH1_ADDR
@ DVGA_TRIM_READBACK_CH1_ADDR
Definition: ADRF6650_Map.h:44
IFLIN_OVERRIDE_ADDR
@ IFLIN_OVERRIDE_ADDR
Definition: ADRF6650_Map.h:54
ATTEN_READBACK_CH1_ADDR
@ ATTEN_READBACK_CH1_ADDR
Definition: ADRF6650_Map.h:42
register_addr_t
register_addr_t
Definition: ADRF6650_Map.h:30
FRAC2_L_SLAVE_ADDR
@ FRAC2_L_SLAVE_ADDR
Definition: ADRF6650_Map.h:98
BLOCK_RESETS_A_ADDR
@ BLOCK_RESETS_A_ADDR
Definition: ADRF6650_Map.h:41
GPO1_CONTROL_ADDR
@ GPO1_CONTROL_ADDR
Definition: ADRF6650_Map.h:66
DVGA_TRIM_READBACK_CH2_ADDR
@ DVGA_TRIM_READBACK_CH2_ADDR
Definition: ADRF6650_Map.h:45
CHIP_TYPE_ADDR
@ CHIP_TYPE_ADDR
Definition: ADRF6650_Map.h:34
MOD_L_ADDR
@ MOD_L_ADDR
Definition: ADRF6650_Map.h:77
FRAC_L_SLAVE_ADDR
@ FRAC_L_SLAVE_ADDR
Definition: ADRF6650_Map.h:100
CP_CURR_ADDR
@ CP_CURR_ADDR
Definition: ADRF6650_Map.h:88
FRAC1_H_ADDR
@ FRAC1_H_ADDR
Definition: ADRF6650_Map.h:73
PHASE_M_SLAVE_ADDR
@ PHASE_M_SLAVE_ADDR
Definition: ADRF6650_Map.h:104
SI_VCO_SEL_ADDR
@ SI_VCO_SEL_ADDR
Definition: ADRF6650_Map.h:83
SIG_PATH_9_NORMAL_ADDR
@ SIG_PATH_9_NORMAL_ADDR
Definition: ADRF6650_Map.h:68
SD_PHASE_L_0_ADDR
@ SD_PHASE_L_0_ADDR
Definition: ADRF6650_Map.h:74
INT_DIV_L_SLAVE_ADDR
@ INT_DIV_L_SLAVE_ADDR
Definition: ADRF6650_Map.h:106
R_DIV_SLAVE_ADDR
@ R_DIV_SLAVE_ADDR
Definition: ADRF6650_Map.h:108
MOD_H_ADDR
@ MOD_H_ADDR
Definition: ADRF6650_Map.h:78
BLOCK_RESETS_ADDR
@ BLOCK_RESETS_ADDR
Definition: ADRF6650_Map.h:65
DVGA_TRIM1_LP3V_OVERRIDE_ADDR
@ DVGA_TRIM1_LP3V_OVERRIDE_ADDR
Definition: ADRF6650_Map.h:56
TDD_BYPASS_ADDR
@ TDD_BYPASS_ADDR
Definition: ADRF6650_Map.h:46
FRAC1_M_ADDR
@ FRAC1_M_ADDR
Definition: ADRF6650_Map.h:72
DVGA_MODE_ADDR
@ DVGA_MODE_ADDR
Definition: ADRF6650_Map.h:49
ADI_SPI_CONFIG_ADDR
@ ADI_SPI_CONFIG_ADDR
Definition: ADRF6650_Map.h:31
DVGA_GAIN2_ADDR
@ DVGA_GAIN2_ADDR
Definition: ADRF6650_Map.h:51
RDIV2_SEL_SLAVE_ADDR
@ RDIV2_SEL_SLAVE_ADDR
Definition: ADRF6650_Map.h:109
DVGA_TRIM2_HP3V_OVERRIDE_ADDR
@ DVGA_TRIM2_HP3V_OVERRIDE_ADDR
Definition: ADRF6650_Map.h:61
DVGA_TRIM1_LP5V_OVERRIDE_ADDR
@ DVGA_TRIM1_LP5V_OVERRIDE_ADDR
Definition: ADRF6650_Map.h:58
DVGA_TRIM2_LP3V_OVERRIDE_ADDR
@ DVGA_TRIM2_LP3V_OVERRIDE_ADDR
Definition: ADRF6650_Map.h:60
BICP_ADDR
@ BICP_ADDR
Definition: ADRF6650_Map.h:89